1. Technical Field of the Invention
The present invention relates to communication systems generally and, in particular, to a method and apparatus for providing differentiated Quality-of-Service guarantees to data transfer sessions in packet switches having multiple contention points.
2. Description of the Background Art
The continuous growth in the demand for diversified Quality-of-Service (QoS) guarantees in broadband data networks introduces new challenges in the design of packet switches that are scalable to large switching capacities. Packet scheduling is the most critical function involved in the provisioning of individual QoS guarantees to the switched packet streams, also referred to as traffic flows. Moreover, present scheduling techniques assume the presence in the switch of a single contention point residing in front of the outgoing links. Such an assumption is not consistent with the highly-distributed nature of many popular architectures for scalable switches, which typically have multiple contention points located in both ingress and egress port cards, as well as in the switching fabric.
Progress has been made in the formalization of theoretical frameworks identifying and characterizing scheduling techniques that are capable of enforcing QoS guarantees for end-to-end packet streams, in terms of one or more of the following: throughput, delay, delay jitter, and fairness. However, most of this work has focused on a single scheduler that operates in isolation to handle traffic flows with a homogenous set of QoS requirements.
Unfortunately, present solutions do not adequately address the adaptation of the available scheduling techniques to the currently dominating switch architectures. Switches that can scale to large aggregate capacities typically feature highly distributed architectures, where the majority of the buffers and basic functionalities are located in the port cards that interface with the incoming and outgoing links. Such decentralized architectures are cost effective, since they can take advantage of low-cost high-density memory technology to implement the buffers, and are desirable due to their ease of implementation, their flexibility in supporting different switch configurations, and their intrinsic modularity in scaling to large switch sizes.